Cost-effectively verify system clocks with JTAG / boundary scan or from an FPGA
A new eBook from ASSET(r) InterTech (www.asset-intertech.com), the leading supplier of tools for embedded instrumentation, explains how cost-effective verification of system clocks during prototype circuit board bring-up and manufacturing can be accomplished with several different methods based on JTAG / boundary-scan testing or IP in an FPGA.
|Testing System Clocks with an FPGA and JTAG | Boundary scan|
Richardson, TX (October 2, 2013) – A new eBook from ASSET® InterTech (www.asset-intertech.com), the leading supplier of tools for embedded instrumentation, explains how cost-effective verification of system clocks during prototype circuit board bring-up and manufacturing can be accomplished with several different methods based on JTAG / boundary-scan testing or IP in an FPGA.
Faulty clocks will simply prevent processors, chipsets, ASICS, FPGAs and all other functional devices from bringing up their operational states. As a result, the operating system and the system’s firmware environment will not boot. By quickly verifying the functionality of the clocks first or relatively early, the engineer can reduce the time needed to bring up prototypes and allow adequate time for more robust functional testing during manufacturing.
“Engineers can quickly rule out faulty clocks as a reason why a circuit board is not booting and they don’t have to rely on expensive oscilloscopes, frequency counters or logic analyzers,” said Kent Zetterberg, product manager at ASSET and author of the eBook. “Non-intrusive board test methods employing instrumentation embedded in chips gives engineers an abundance of new and less costly alternatives. Boundary scan / JTAG is a powerful way to tap into the capabilities of embedded instrumentation.”
The new eBook is titled “Testing System Clocks with Boundary Scan (JTAG) and an FPGA.” It can be downloaded directly from the ASSET InterTech website at: www.asset-intertech.com/Products/Boundary-Scan-[...] . Other informative eBooks, white papers, case studies, application notes and videos on JTAG, IJTAG, hardware-assisted software debug, embedded instrumentation and other topics relating to board and chip debug, validation and test can be downloaded from the eResources section of the web site at: www.asset-intertech.com/eResources
About ASSET InterTech
ASSET InterTech is a leading supplier to the electronics industry of tools based on embedded instrumentation. Its ScanWorks platform overcomes the limitations of external test and measurement equipment by applying instrumentation embedded in semiconductors to perform chip and circuit board debug, design validation, manufacturing test and field support. ASSET’s recent acquisition of Arium, Inc., adds a powerful suite of firmware debug and trace tools to the ScanWorks platform. ASSET InterTech is located at 2201 North Central Expressway, Suite 105, Richardson, TX 75080.
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