How to preserve signal-chain integrity when interfacing microcontrollers with DACs
One way to manage power is to reduce the supply voltage. A decade ago, industrial control systems used 5 V microcontrollers. Now, with more processing capability inside the microcontroller, 3.3 V microcontrollers are gaining in popularity because this increased processing power coupled with lower supply voltage can lead to increased power savings.
On a high level, this shift in power supply seems like an easy solution to the power dissipation problem. However, microcontrollers are tightly coupled with all of the other components that they control. System architects have to ensure that all components are compatible with the logic-level interfacing requirement while not compromising the integrity of the signal chain’s precision. In addition to this requirement, the system must be power efficient. The following discussion will highlight some of the challenges of interfacing microcontrollers with precision digital-to-analog converters (DACs) and how to address them.
There are multiple power-supply domains for typical non-isolated industrial systems (Figure 1). The microcontroller is powered by a high-capacity power supply capable of delivering hundreds of milliamperes of current. Precision components such as DACs require a clean power supply that need not provide high current.
The requirement of the application mandates the DAC’s power supply voltage level. For example, many precision applications require a 5 V output voltage range. This means that the power supply must be adequate to support this output range. Thus, in Figure 1, VDD-DAC must be > 5 V. For the lowest power dissipation, the lowest power supply must supply the microcontroller. Most common microcontrollers can operate with a 3 V power supply. Hence, VDDM can be as low as 3 V.
This power supply requirement places an unusual constraint on DACs. The DAC must be able to accept the input digital signal that toggles between 0 V and 3 V while itself being powered by a 5 V supply. Every precision DAC has a specification that relates to this condition, typically listed under the logic inputs section of the characteristics table (Figure 2).
The specification of importance in this case is VINH (input high voltage). According to the data sheet, theis specified to accept input digital signals from 0.7 x AVDD to AVDD for 2.7 V ≤ AVDD ≤ 5.5 V. Using the power supply requirement from Figure 1, the input digital signal must be ≥ 3.5 V (0.7 x 5) to use this DAC. This places a lower limit on the microcontroller power supply: 3.5 V. But to reduce the power dissipation in the microcontroller, it is imperative to use the lowest possible power supply – for example, 3 V. This discrepancy is a common problem for system architects.
There are three solutions to this problem.
Use a level shifter
A level shifter converts digital signals from one logic level to another. Using a level shifter between the microcontroller and the DAC (Figure 3) is the simplest workaround. But because each digital input signal needs a dedicated level shifter, this solution increases total board size and cost, particularly for DACs with multiple digital input pins like the DAC8568. The level shifter must be functional at the required communication speed between the microcontroller and the DAC.
Choose a DAC with an integrated level shifter
Some DACs have the level shifter integrated, with a separate power supply pin called the IOVDD (Figure 4). The package size of the DAC increases slightly with the additional pin, thereby increasing the board area. This solution also requires isolating the IOVDD power supply for power-isolated systems, including additional power isolators.
Choose a DAC with a transistor-transistor logic (TTL)-enabled interface
Some DACs have an interface that accepts lower levels of VINH. For example, the(Figure 5) data sheet specifies that it can accept input digital signals from 2.1 V to AVDD for 2.7 V ≤ AVDD ≤ 5.5 V. Thus, you can use this DAC in systems such as Figure 1 with VDDM = 3 V and VDD-DAC = 5 V.
There are three key priorities while designing a system with a DAC that has a TTL-enabled interface.
By using a TTL-enabled logic interface, the microcontroller can now run at the lower 3 V supply voltage. However, based on the idle voltage of the input digital signal to the DAC, there can be significant leakage current that flows through the power supply of the DAC. The typical value for this leakage current is usually specified in the power requirements section of the characteristics table (Figure 6).
The DAC power supply of 5 V coupled with the pin-idling voltage of 3 V causes a significant increase in the device’s current consumption. The majority of the leakage current flows through the I/O cells, as shown in Figure 7. This is evident from the table in Figure 5. In order to reduce this leakage current, we recommend keeping all digital input signals (except level-sensitive signals) idling at logic low or 0 V as opposed to logic high or 3 V.
DAC’s DC accuracy
DC accuracy is a key point that is often overlooked while interfacing a microcontroller and a precision DAC with TTL logic. Figure 8 shows a simplified block diagram of a precision DAC. The parasitic resistor, RPAR, on the supply (VDD) and ground represents the pin and metal resistances inside the chip. In most precision DACs with a single supply and ground pin (for example, the), the analog and I/O power supplies are shared internally.
Typically, the power supply lines inside the chip are directly connected to the supply pin; however, this is not always possible on very small packages. In those cases, the analog power supply is tapped from the closest point on the power supply rail. Thus, the analog power supply to the DAC output buffer incurs parasitic resistance to the supply pin.
The leakage current discussed in section (a) causes IR drop across the parasitic resistance on the power and ground rails, reducing the headroom and foot room for the DAC output buffer and affecting DAC DC specifications such as offset and zero-code error. To reduce this impact, we recommend keeping all digital input signals (except level-sensitive signals) idling at logic low or 0 V, as opposed to logic high or 3 V.
Monotonicity and INL
For precision DACs, monotonicity and integral non-linearity (INL) are guaranteed for all of the codes. Following the example in Figure 8, the magnitude of ILEAK depends on the number of signals idling at logic high. The ILEAK is largest when all of the signals are idling at logic high. In between subsequent writes to the DAC, if the different numbers of input signals are idling at logic high or low, the magnitude of ILEAK will vary from code to code.
This can cause changes in the headroom and foot room for the DAC output buffer and affect code-to-code linearity or even non-monotonic behavior of the DAC output in the worst case. We recommend keeping all digital inputs at the same I/O levels before and after writing to the DAC.
Preserving precision in a signal chain is often considered a part of signal-chain conditioning. However, interfacing the microcontroller and precision components in order to maintain precision in the signal chain also requires special care. This article discussed the issues associated with interfacing two different I/O levels between the microcontroller and precision DACs, along with some techniques to reduce the impact of interfacing to the precision signal chain.
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