Building an FPGA-based solution for industrial wireless sensor networks
With the introduction of wireless field-side standards WirelessHART and SP100.11a, gateway implementers must make difficult trade-offs between the cost of a solution and the requirement for it to communicate with the plant over multiple Industrial Ethernet standards. With more intelligence moving into networked/gateway units, designers need reliable, proven solutions as building blocks for successful implementations in the evolving standards landscape. Robust solutions that can support any plant network protocol can be delivered using FPGAs, embedded processors, Intellectual Property (IP), and software protocol stacks.
Figure 1 illustrates a network manager/gateway system containing field-side radio modules for wireless communication, a core system processor, and a communication coprocessor with an internal (soft) embedded processor implemented in an FPGA. FPGAs provide a flexible platform that offloads the task of communication over the plant network, freeing up the core system processor to handle the countless tasks of managing the network, ensuring secure communication, and more.
Implementing a universal Industrial Ethernet solution
Engineering a solution to support multiple plant-side Industrial Ethernet protocols can be achieved by creating a series of plug-in boards, one for each protocol. But with the number of standards being utilized worldwide and their continual evolution, this solution cannot offer fast turnaround times or cost effectiveness.
Furthermore, the existing CPU might not have the performance/hardware required to support new features/protocols, and an off-the-shelf protocol stack might not be available. Re-coding software to support a new processor/stack is expensive and takes a long time. Where new CPUs or Industrial Ethernet ASIC/ASSP devices are required, new circuit boards must be developed. As each Industrial Ethernet protocol evolves, new hardware might be required, mandating support for multiple versions of the board and planning for the potential obsolescence of the ASIC/ASSP devices. This type of solution is likely to be expensive, difficult to support, and slow to deliver new features.
However, the flexibility of FPGAs enables designers to deliver a board with multistandard Industrial Ethernet capability. FPGAs can be reconfigured easily so one circuit board can be programmed to support any Industrial Ethernet protocol at any time, right up until product shipment. If a different protocol is needed, simply re-program the FPGA. This can be done easily in just seconds with the required FPGA configuration file.
All of the Ethernet functions above the physical layer (Layer 1) are implemented in the FPGA. A Media Access Controller (MAC, Layer 2) is implemented in programmable FPGA logic, and the higher-level functions (Layer 3 and above) are implemented in software running on a processor core also built using the FPGA logic.
Implementing a communication channel between the existing application processor and the FPGA is easy because of the programmability of the FPGA logic, the multistandard support of the I/O pins, and the availability of a wide range of off-the-shelf interface IP. Generally, a designer can use an existing communication facility in the processor device (such as I2C, SPI, or another local parallel bus) or system (PCI, PCI Express, CANopen, or other) to communicate with the FPGA. This approach has the additional advantage of requiring minimal computing time and changes to the application software running on the existing processor.
In an FPGA, a designer can easily create a system that contains two or more soft microprocessor cores, enabling the integration of application processing into the FPGA if advantageous (see Figure 2). This type of system integration reduces component count, cost, and power consumption. Additionally, because the design is now entirely IP-based, it is protected against obsolescence due to the long lifetime of FPGAs and the ability to easily migrate the design to newer generations of FPGAs.
The flexibility of FPGAs also enables designers to implement new interfaces in the system. These can be simple or more complex communication interfaces, such as support for new memory standards like DDR2/3 or the latest communication technologies like Bluetooth and PCI Express.
FPGA design flow
FPGA configuration files are generated by tool suites such as Altera’s Quartus II development software. This software delivers everything needed to design, modify, and generate FPGA configurations (shown in Figure 3) using VHDL, Verilog, schematic, graphical, or block-based design methodologies.
The design environment offers very high levels of productivity compared to traditional FPGA design flows by supporting features such as interfaces to hardware simulation tools, hardware runtime debug tools, and system performance and power optimization capabilities.
Building the FPGA-based design
Thanks to the availability of prebuilt processor and Ethernet MAC IP components, it is easy to create a custom processor and Ethernet MAC hardware design using the System On a Programmable Chip (SOPC) Builder tool included in the Quartus II suite. This Graphical User Interface (GUI)-driven tool facilitates easy IP-based design creation and accelerates/automates IP-based system configuration, integration, and generation. As the IP is pre-built and tested, and the tool generates all of the HDL for a working system, no hand-coding is required. As the IP/system interconnect is machine generated, the design is correct by construction. Once the system is generated, it is easily compiled to create a configuration file that can then be downloaded into the FPGA.
If a new or modified design is needed, the design is easily updated using the GUI; then the system can be regenerated and recompiled. Hence, creating a hardware design to support a new Industrial Ethernet protocol can be done by simply purchasing the IP required, dropping it into the existing system design, and regenerating it. One click to recompile and the hardware design is ready.
IP packages for many different Industrial Ethernet protocols are available today, including Modbus IDA, EtherNet/IP, PROFINET, Ethernet POWERLINK, SERCOS III, VARAN, and EtherCAT. Hardware IP is generally packaged as a SOPC Builder component that contains the MAC and any additional logic required. The software IP is delivered as a library or software API written in C for the Nios II embedded processor.
Getting the most leverage
The easiest way to start a project is to use an Industrial Ethernet development kit, and many vendors offer proven development board solutions and reference designs for Industrial Ethernet systems. These boards carry a low-cost FPGA and dual-channel IEEE 802.3 Layer 1 Ethernet communication hardware, making them Industrial Ethernet protocol independent. The board might also carry transceivers for other interfaces like CAN, USB, UART, and LVDS.
The advent of low-cost FPGAs, soft microprocessor IP, and pre-built Industrial Ethernet hardware with supporting software IP has enabled the development of a single programmable solution for interfacing wireless systems to any Industrial Ethernet plant network. FPGAs support any Ethernet-based industrial communication protocol from the same hardware and provide all of the system integration, flexibility, and obsolescence protection benefits that come with programmable devices. Additional development advantages of an FPGA implementation come from the development tools that offer a single integrated environment and deliver fast development, easy-to-maintain systems, and a quick, easy way to create an Industrial Ethernet-based design with minimal effort.
Stefano Zammattio is a member of the European technical product marketing team at Altera (based in[s1] the UK, with corporate headquarters in San Jose, California), which he joined in 2004. He is responsible for Altera’s embedded and industrial products in the European region, specializing in the Nios II processor and SOPC Builder products. He has been involved in the computing and electronics industry since 1987 and holds a BSc in Physics from the University of Essex and an MSc in Medical Electronics from the University of London.